Design optimization of ESD protection and latchup prevention for a serial I/O IC

ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/ O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness.

[1]  Ronald R. Troutman,et al.  Latchup in CMOS Technology: The Problem and Its Cure , 1986 .

[2]  J. W. Meredith,et al.  Microelectronics reliability , 1988, IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'.

[3]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[4]  Yeh-Ning Jou,et al.  A compact model of holding voltage for latch-up in epitaxial CMOS , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[5]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .

[6]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[7]  Ming-Jer Chen,et al.  Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I-V characteristics in NMOS devices , 2001 .

[8]  Michael C. Smayling,et al.  Efficient npn operation in high voltage NMOSFET for ESD robustness , 1995, Proceedings of International Electron Devices Meeting.

[9]  Chung-Yu Wu,et al.  ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure , 1995, Proceedings of International Electron Devices Meeting.