Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals

In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP's Long Term Evolution (LTE). This concept already demonstrated a significant performance benefit over conventional approaches by on-the-fly header decoding and deciphering for the data plane of the LTE protocol stack layer 2 in downlink direction. With a low-level hardware implementation we prove that also from an architectural point of view the sDMA controller is suitable for LTE terminals. Compared to conventional hardware acceleration, chip area and energy consumption are reduced by 10% and 56%, respectively. Furthermore, we show that the header decoding has the highest architectural impact on the sDMA controller. By a change of the hardware/software partitioning within the header decoding unit, the chip area of the sDMA controller is decreased by 35%, while it consumes 39% less power. The improvement compared to the conventional approach (with the same modification) is then even increased to 17% (area) and 59% (energy).

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