A 500 Mb/s/pin quadruple data rate SDRAM interface using a skew cancellation technique

The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved accordingly in spite of quadrupled increase in the memory density every three years. This imbalance requires memory systems to use a wide data-bus and/or a high-speed I/O interface to increase access speed. Increasing access speed with a wide data-bus is studied, but is practically limited by memory pin counts. Alternatively, Rambus DRAM (RDRAM) achieves access speed up to 800 MB/s in a well-controlled printed circuit board (PCB) environment by adopting a high-speed I/O interface. Low cost systems use synchronous DRAM (SDRAM) interface because they cannot afford a high-cost PCB. This system limits memory access speed to the system clock speed, which is commonly less than 100 MHz. Double data rate (DDR) SDRAM, is twice as fast as SDRAM memory access by taking both rising and falling edges of the system clock, while keeping the SDRAM interface. To deal with clock skew, the DDR SDRAM provides an extra strobe signal for the receiving end.

[1]  Y. Takai,et al.  A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme , 2000, IEEE Journal of Solid-State Circuits.

[2]  Soo In Cho,et al.  A 2.5 V 333 Mb/s/pin 1 Gb double data rate SDRAM , 1999 .

[3]  Paul R. Gray,et al.  A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS , 1990 .

[4]  T. Jung,et al.  A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[5]  P. Batra,et al.  A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[6]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[7]  J. Lee,et al.  A 250 MHz low jitter adaptive bandwidth PLL , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).