Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks.

[1]  Majid Sarrafzadeh,et al.  On Computation and Resource Management in Networked Embedded Systems , 2003 .

[2]  Peter Y. K. Cheung,et al.  Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis , 2007, FPGA '07.

[3]  Narayanan Vijaykrishnan,et al.  Variation-aware task allocation and scheduling for MPSoC , 2007, ICCAD 2007.

[4]  Xiaoyao Liang,et al.  Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[5]  Srivaths Ravi,et al.  Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[6]  Taewhan Kim,et al.  Timing variation-aware high-level synthesis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Peter Marwedel,et al.  Analysis of the influence of register file size on energyconsumption, code size, and execution time , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Xiaoxia Wu,et al.  Variability-driven module selection with joint design time optimization and post-silicon tuning , 2008, 2008 Asia and South Pacific Design Automation Conference.

[9]  Narayanan Vijaykrishnan,et al.  Variation-aware task allocation and scheduling for MPSoC , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Jason Cong,et al.  Synthesis of an application-specific soft multiprocessor system , 2007, FPGA '07.

[11]  Frank Vahid,et al.  A highly configurable cache architecture for embedded systems , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[12]  David M. Brooks,et al.  Mitigating the Impact of Process Variations on Processor Register Files and Execution Units , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).