VEAP: Global optimization based efficient algorithm for VLSI placement

In this paper we present a very simple, efficient while effective placement algorithm for Row-based VLSIs. This algorithm is based on strict mathematical analysis, and provably can find the global optima. From our experiments, this algorithm is one of the fastest algorithms, especially for very large scale circuits. Another point desired to point out is that our algorithm can be run in both wirelength and timing-driven modes.

[1]  Brian W. Kernighan,et al.  A Procedure for Placement of Standard-Cell VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1993, ICCAD.

[3]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  G. J. Wipfler,et al.  A Combined Force and Cut Algorithm for Hierarchical VLSI Layout , 1982, 19th Design Automation Conference.

[5]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[6]  Frank M. Johannes,et al.  On the Relative Placement and the Transportation Problem for Standard-Cell Layout , 1986, 23rd ACM/IEEE Design Automation Conference.

[7]  C. Sechen,et al.  New algorithms for the placement and routing of macro cells , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Ernest S. Kuh,et al.  Proud: a fast sea-of-gates placement algorithm , 1988, DAC '88.

[9]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[10]  Stephen W. Director,et al.  Mason: A Global Floorplanning Approach for VLSI Design , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Chung-Kuan Cheng,et al.  Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  John P. Blanks Near-Optimal Placement Using a Quadratic Objective Function , 1985, 22nd ACM/IEEE Design Automation Conference.

[13]  Arvind Srinivasan,et al.  RITUAL: a performance driven placement algorithm for small cell ICs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[14]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[15]  G. Kedem,et al.  An algorithm for quadrisection and its application to standard cell placement , 1988 .