Dynamic module partitioning for library based placement on heterogeneous FPGAs

Library based design and IP reuse have been previously proposed to speed up the synthesis for large-scale FPGA designs. However, previous library based design flow faces several unresolved challenges. Firstly, they may result in large waste area between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce the waste area, pre-synthesis each module for different ratios is time consuming and would require a large library. Secondly, when the targeting FPGA architecture changes, a new library is needed to best fit the targeting architecture. Re-synthesizing the library for different architectures is not feasible. To address these challenges, in this paper, we propose a dynamic module partitioning approach for the library based design flow to dynamically generate the appropriate shape of modules based on single-ratio modules in the library while efficiently utilizing the pre-placement module information. A set of rules are developed to select the most suitable module and determine the partition to minimize the area and delay of the placement without increasing much of the synthesis time. The proposed approach can adapt to different architectures and also address the fixed-outline constraint. Experiment results show that our approach can reduce the area by up to 10% with reasonably increased delay under acceptable runtime.