Efficient variability analysis of arithmetic units using linear regression techniques

The performance of modern digital signal processing (DSP) systems is inherently affected by the variability tolerance of their main arithmetic units. As CMOS technology approaches nanometer scales, numerous threats for the reliability of DSP designs emerge. A large portion of these phenomena are related to threshold voltage $$V_{th}$$Vth variations, resulting in timing failures due to an overall increase of the arithmetic unit delay. In this work, we employ linear regression techniques to accelerate transistor variability estimation using static timing analysis (STA) tools. By identifying the variation-critical part of an arithmetic circuit, we reduce the transistor inventory that needs to be tracked by the STA solver. We substantiate the efficiency of the proposed framework for realistic designs. For the main logic blocks of the modulo $$2^n-1$$2n-1 add–multiply (AM) operation, we capture the variability-induced degradation of the Modified Booth (MB) encoding stage with negligible accuracy losses. We also exploit our methodology as a useful aid for variability-aware design techniques and we investigate the variability-tolerance of novel MB recoding schemes against conventional designs.