A Self-Aligned InGaAs HEMT Architecture for Logic Applications

In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its future scaling capabilities. We find that, as the insulator is scaled to achieve enhancement mode, the performance of the device is limited by degradation of the I ON/I OFF ratio due to gate leakage current. By use of TLM test structures, we have determined that the barrier resistance dominates the source resistance. We use a trilayer TLM model to predict the expected evolution of the contact resistance as it is scaled to realistic VLSI dimensions and find that the current technology results in resistance values that are two orders of magnitude higher than the desired target for sub-22-nm nodes. Using the model, we explore different options for device redesign. Both I ON/I OFF and source-resistance limitations imply that the use of a high-k gate dielectric will be required for future device implementations.

[1]  N. Waldron,et al.  90 nm Self-aligned Enhancement-mode InGaAs HEMT for Logic Applications , 2007, 2007 IEEE International Electron Devices Meeting.

[2]  I. Watanabe,et al.  547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance , 2004, IEEE Electron Device Letters.

[3]  Kwang-Seok Seo,et al.  The Impact of Side-Recess Spacing on the Logic Performance of 50 nm InGaAs HEMTs , 2006, 2006 International Conference on Indium Phosphide and Related Materials Conference Proceedings.

[4]  T. Enoki,et al.  High-performance 0.1-/spl mu/m-gate enhancement-mode InAlAs/InGaAs HEMTs using two-step-recessed gate technology , 1998, Conference Proceedings. 1998 International Conference on Indium Phosphide and Related Materials (Cat. No.98CH36129).

[5]  Osaake Nakajima,et al.  Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded InxGa1-xAs Layers , 1988 .

[6]  Kwang-Seok Seo,et al.  Performance Evaluation of 50 nm In0.7Ga0.3As HEMTs For Beyond-CMOS Logic Applications , 2005 .

[7]  Tetsuya Suemitsu,et al.  High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology , 1999 .

[8]  M. Tokumitsu,et al.  Lateral Scale Down of InGaAs/InAs Composite-Channel HEMTs With Tungsten-Based Tiered Ohmic Structure for 2-S/mm $g_{m}$ and 500-GHz $f_{T}$ , 2007, IEEE Transactions on Electron Devices.

[9]  April Brown,et al.  Novel high performance self-aligned 0.15 micron long T-gate AlInAs-GaInAs HEMTs , 1989, International Technical Digest on Electron Devices Meeting.

[10]  J.A. del Alamo,et al.  Scaling Behavior of In0.7Ga0.3As HEMTs for Logic , 2006, 2006 International Electron Devices Meeting.

[11]  Jonathan K. Abrokwah,et al.  Nonalloyed InGaAs/GaAs ohmic contacts for self‐aligned ion implanted GaAs heterostructure field effect transistors , 1992 .

[12]  R. Chau,et al.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.

[13]  Jesús A. del Alamo,et al.  Beyond CMOS: Logic Suitability of In0.7Ga0.3As HEMT , 2006 .

[14]  J.A. del Alamo,et al.  Lateral and Vertical Scaling of $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications , 2008, IEEE Transactions on Electron Devices.

[15]  B. Harrison,et al.  An analytical model for alloyed ohmic contacts using a trilayer transmission line model , 1995 .

[16]  Tetsuya Suemitsu,et al.  30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs , 2002 .

[17]  Iain G. Thayne,et al.  Self-aligned T-gate InP HEMT realisation through double delta doping and a non-annealed Ohmic process , 2004 .

[18]  T. Mimura,et al.  Importance of gate-recess structure to the cutoff frequency of ultra-high-speed InGaAs/InAlAs HEMTs , 2002, Conference Proceedings. 14th Indium Phosphide and Related Materials Conference (Cat. No.02CH37307).

[19]  S. Natarajan,et al.  A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[20]  Kwang-Seok Seo,et al.  Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyond-CMOS logic applications , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[21]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part I: Historical Trends , 2008, IEEE Transactions on Electron Devices.

[22]  Stephen J. Pearton,et al.  Low bias dry etching of tungsten and dielectric layers on GaAs , 1993 .

[23]  Dae-Hyun Kim,et al.  Logic Suitability of 50-nm $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Beyond-CMOS Applications , 2007, IEEE Transactions on Electron Devices.

[24]  末光 哲也.  Study of Sub-0.1-μm Gate InP-Based High Electron Mobility Transistors , 2000 .

[25]  Mark J. W. Rodwell,et al.  Low resistance, nonalloyed Ohmic contacts to InGaAs , 2007 .

[26]  T. Kobayashi,et al.  Device technologies for InP-based HEMTs and their application to ICs , 1994, Proceedings of 1994 IEEE GaAs IC Symposium.

[27]  K. Elgaid,et al.  50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node , 2006, IEEE Transactions on Electron Devices.

[28]  Naohito Yoshida,et al.  Alloyed and Non-Alloyed Ohmic Contacts for AlInAs/ InGaAs High Electron Mobility Transistors , 1994 .

[29]  T. Holbrook,et al.  References , 1964 .

[30]  Taketo Kunihisa,et al.  A novel high-performance WSi-gate self-aligned N-AlGaAs/InGaAs/N-AlGaAs pseudomorphic double heterojunction MODFET by ion implantation , 1998, Compound Semiconductors 1997. Proceedings of the IEEE Twenty-Fourth International Symposium on Compound Semiconductors.