A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- $\mu\hbox{m}$ CMOS
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[1] C. Gendarme,et al. CMOS Circuit Design, Layout, and Simulation, 2nd edition [Book Review] , 2006, IEEE Circuits and Devices Magazine.
[2] F. Kuttner. A 1.2V 10b 20MS/S Non-Binary Successive Approximation ADC in 0.13μm CMOS , 2002 .
[3] T. O. Anderson,et al. Optimum Control Logic for Successive Approximation Analog-to-Digital Converters , 1972 .
[4] Eric A. M. Klumperink,et al. A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[5] Naveen Verma,et al. Ultralow-power electronics for biomedical applications. , 2008, Annual review of biomedical engineering.
[6] Chung-Ming Huang,et al. A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[7] Franz Kuttner,et al. A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[8] R.W. Brodersen,et al. A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS , 2006, IEEE Journal of Solid-State Circuits.
[9] Hao-Chiao Hong,et al. A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC , 2007, IEEE Journal of Solid-State Circuits.
[10] Robert W. Brodersen,et al. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .
[11] Hong-June Park,et al. A 1.3μW 0.6V 8.7-ENOB successive approximation ADC in a 0.18μm CMOS , 2009, 2009 Symposium on VLSI Circuits.
[12] Nobukazu Takai,et al. SAR ADC algorithm with redundancy , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.