FPGA Based Pipelined Controller Design and Implementation

The proposed architecture is for the design, development and implementation of a 16-bit 4 stage pipelined Reduced Instruction Set Computer (RISC) IP core. In this paper it is represented as pipelined controller. It is observed that the pipelined architecture is efficient and by micro-architecture tweaking the execution time can be reduced for the pipelined instruction execution. The architecture presented in this paper is designed by using mainly three units and they are instruction memory, data memory and pipelined controller. The pipelined controller is designed by using four units and they are fetch unit, decode unit, execute unit and internal register unit. The major emphasis of this paper is to design and implement the 4 stage pipelined controller on FPGA. The pipelined controller design is implemented using Verilog RTL. In addition to the pipelined feature the design is having programmable register selections and data transfer mechanism. The pipelined controller is synthesized using Altera Quartus II and verified by using QuestaSim. The design is implemented by using Altera Cyclone II FPGA EP2C20F484C7 Keywords—FPGA, Verilog, pipelining, Resource Sharing, Logic Duplication., Opcode, RISC