论文信息 - Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunneling Field Effect Transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing. Firstly, the impact of the gate oxide thickness and implant doping conditions on the tunneling performance is analyzed and compared with TCAD simulations. Secondly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). Surprisingly, the SPER anneal shows a strong enhanced tunneling current with a record drive current of 46µA/µm at VDD of −1.2V and IOFF of 5pA/µm for Si pTFETs.

[1] K. Boucart,et al. Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs , 2009, IEEE Electron Device Letters.

[2] K. Maex,et al. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization , 2008 .

[3] Yee-Chia Yeo,et al. Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications , 2008 .

[4] K. Boucart,et al. Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric , 2007 .

[5] R. Rooyackers,et al. Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width , 2010 .

[6] K. Boucart,et al. Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric , 2006, 2006 European Solid-State Device Research Conference.

[7] G. Amaratunga,et al. Silicon surface tunnel transistor , 1995 .

[8] J. Appenzeller,et al. Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design , 2005, IEEE Transactions on Electron Devices.

[9] J. Kittl,et al. Ni based silicides for 45 nm CMOS and beyond , 2004 .