Junctionless Impact Ionization MOS: Proposal and Investigation

We propose a novel junctionless impact ionization MOS (JIMOS) on a p-type silicon film using charge plasma concept. This device does not have metallurgical junctions and requires no impurity doping for creating the source and drain. This makes the JIMOS combine the benefits of an impact ionization MOS (IMOS) (steep subthreshold slope) and a junctionless field-effect transistor (JLFET) (low thermal budget process). Using 2-D simulations, we show that the performance of the JIMOS is analogous to that of a corresponding IMOS in which the source and drain regions are created by impurity doping. The proposed idea can pave the way for fabricating the IMOS using a low thermal budget process similar to that of a JLFET.

[1]  M. Jagadesh Kumar,et al.  Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation , 2014, Journal of Display Technology.

[2]  Jawar Singh,et al.  Charge-Plasma Based Process Variation Immune Junctionless Transistor , 2014, IEEE Electron Device Letters.

[3]  M. J. Kumar,et al.  Doping-Less Tunnel Field Effect Transistor: Design and Investigation , 2013, IEEE Transactions on Electron Devices.

[4]  M. J. Kumar,et al.  Schottky Collector Bipolar Transistor Without Impurity Doped Emitter and Base: Design and Performance , 2013, IEEE Transactions on Electron Devices.

[5]  B. Ghosh,et al.  Junctionless Tunnel Field Effect Transistor , 2013, IEEE Electron Device Letters.

[6]  M. J. Kumar,et al.  Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device , 2012, IEEE Transactions on Electron Devices.

[7]  Ru Huang,et al.  Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage , 2011 .

[8]  N. Singh,et al.  A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor , 2010, IEEE Electron Device Letters.

[9]  Bijoy Rajasekharan,et al.  Fabrication and Characterization of the Charge-Plasma Diode , 2010, IEEE Electron Device Letters.

[10]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[11]  C. Salm,et al.  The Charge Plasma P-N Diode , 2008, IEEE Electron Device Letters.

[12]  Yee-Chia Yeo,et al.  A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance , 2008, IEEE Electron Device Letters.

[13]  Guo-Qiang Lo,et al.  Strain and Materials Engineering for the I-MOS Transistor With an Elevated Impact-Ionization Region , 2007, IEEE Transactions on Electron Devices.

[14]  Sang Wan Kim,et al.  Breakdown voltage reduction in I-MOS devices , 2006, 2006 IEEE Nanotechnology Materials and Devices Conference.

[15]  G. W. Smith,et al.  Non-local aspects of breakdown in pin diodes , 1995 .

[16]  P. Griffin,et al.  A Novel Depletion-IMOS (DIMOS) Device With Improved Reliability and Reduced Operating Voltage , 2009, IEEE Electron Device Letters.

[17]  K. Gopalakrishnan,et al.  Impact ionization MOS (I-MOS)-Part II: experimental results , 2005, IEEE Transactions on Electron Devices.

[18]  P.B. Griffin,et al.  Impact ionization MOS (I-MOS)-Part I: device and circuit simulations , 2005, IEEE Transactions on Electron Devices.