A Phase Change Memory Cell With Metal Nitride Liner as a Resistance Stabilizer to Reduce Read Current Noise for MLC Optimization

Relatively large noise of phase change material is one of the obstacles for realization of multilevel cell (MLC) using phase change memory (PCM) technology. We experimentally verify that the noise in PCM can be lowered as much as ~4 times by a novel PCM cell which utilizes metal nitride liner to provide an alternative conductive path to the amorphous region with large noise. Program-and-verify (PNV) simulation based on noise measurement data confirms that the small noise of a PCM cell with metal nitride liner improves the MLC performance either by reducing number of PNV iterations or bit-error rate.

[1]  D. Ielmini,et al.  Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation , 2007, 2007 IEEE International Electron Devices Meeting.

[2]  M. Breitwisch,et al.  Novel Lithography-Independent Pore Phase Change Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[3]  K. Suu,et al.  Crystalline-as-deposited ALD phase change material confined PCM cell for high density storage class memory , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[4]  Kailash Gopalakrishnan,et al.  Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..

[5]  I. Flinn.  Extent of the 1/f Noise Spectrum , 1968, Nature.

[6]  F. Pellizzer,et al.  Characterization and modelling of low-frequency noise in PCM devices , 2008, 2008 IEEE International Electron Devices Meeting.

[7]  Evangelos Eleftheriou,et al.  Projected phase-change memory devices , 2015, Nature Communications.

[8]  C. Hagleitner,et al.  Device, circuit and system-level analysis of noise in multi-bit phase-change memory , 2010, 2010 International Electron Devices Meeting.

[9]  Y.N. Hwang,et al.  MLC PRAM with SLC write-speed and robust read scheme , 2010, 2010 Symposium on VLSI Technology.

[10]  C. Lam,et al.  A phase change memory cell with metallic surfactant layer as a resistance drift stabilizer , 2013, 2013 IEEE International Electron Devices Meeting.

[11]  H.-S. Philip Wong,et al.  Phase Change Memory , 2010, Proceedings of the IEEE.

[12]  Victor G. Karpov,et al.  Possible mechanisms for1/fnoise in chalcogenide glasses: A theoretical description , 2009 .

[13]  S. Raoux.  Phase Change Materials , 2009 .

[14]  Luca Larcher,et al.  Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices , 2009 .

[15]  Haralampos Pozidis,et al.  Multilevel-Cell Phase-Change Memory: A Viable Technology , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[16]  F. Hooge,et al.  Lattice scattering causes 1/ƒ noise , 1978 .

[17]  A. Pirovano,et al.  Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials , 2004, IEEE Transactions on Electron Devices.

[18]  G. Spadini,et al.  The Role of Interfaces in Damascene Phase-Change Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[19]  Haralampos Pozidis,et al.  Programming algorithms for multilevel phase-change memory , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[20]  K. Gopalakrishnan,et al.  Phase change memory technology , 2010, 1001.1164.

[21]  P. Fantini,et al.  $\hbox{1}/f$ Noise in 45-nm RESET-State Phase-Change Memory Devices: Characterization, Impact on Memory Readout Operation, and Scaling Perspectives , 2012, IEEE Electron Device Letters.

[22]  S.O. Park,et al.  Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation , 2007, 2007 IEEE Symposium on VLSI Technology.