Implementation of miller sub-carrier modulation codec by FPGA

In the UHF literacy inverter system design based on ISO/IEC18000-6C protocol,miller sub-carrier modulation encoding and decoding design is the key technology.First,the encoding and decoding characteristics of miller sub-carrier modulation is reseached.Then a miller sub-carrier modulation encoding and decoding design based on FPGA and Verilog HDL language is designed and realized by EP1C12Q chip belonging to Cyclone I series of Altera Company.Simulation results show that the Miller sub-carrier modulation r encoding and decoding design based on FPGA can make the encode and decode module output exactly right and process speedly,and encoding and decoding design meets high efficiency,extensible,convenient integration and so on.