Noise tunable clock delayed domino logic using latched keeper

In this work, domino logic with a latched keeper technique is proposed. The circuit, which is used to implement the technique, utilizes a latch with standard domino. By using the simple structure, we can obtain better performance, noise immunity, and lower power consumption. The simulation results for a 65 nm CMOS technology show an improvement between 5% and 55.7% in delay and 8% and 15% in power consumption, over its previous suggestions.

[1]  Eby G. Friedman,et al.  Domino logic with variable threshold voltage keeper , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Sung-Mo Kang,et al.  Skew-tolerant high-speed (STHS) domino logic , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[3]  Sung-Mo Kang,et al.  Low power and high performance circuit techniques for high fan-in dynamic gates , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[4]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[5]  A. Alvandpour,et al.  A leakage-tolerant multi-phase keeper for wide domino circuits , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[6]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[7]  Mohamed I. Elmasry,et al.  High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).