A CAD system for the design of field programmable gate arrays

Field Programmable Gate Arrays (FPGA’s) are a relatively new type of chip. This paper describes the software necessary to support two distinct but closely related aspects of them: the development of a new FPGA architecture, and the use of FPGA’s from an application viewpoint. The basic CAD support structure consists of a set of file formats and programs that successively bind and evaluate design decisions. The FPGA designer starts by specifying a block architecture as a schematic. This is analyzed, manipulated, and condensed into a set of files that characterize the routing capabilities and programming requirements of the proposed FPGA design. The application designer specifies a circuit in a standard format (SLIF). This is bound to the resources available in the generic FPGA. The result is a configuration file that maps the application onto the proposed FPGA fabric. During FPGA development, the efficiency of this mapping can be analyzed, and the architecture modified. Once the FPGA has been fabricated, the configuration data can be sent to the actual hardware.