Systematic Design of High‐Resolution High‐Frequency Cascade Continuous‐Time Sigma‐Delta Modulators

This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigmadelta (ΣΔ) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT ΣΔ modulator in a 1.2 V 130 nm CMOS technology.

[1]  Alex Doboli,et al.  High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Francisco V. Fernández,et al.  High-Level Synthesis of Switched-Capacitor , Switched-Current and Continuous-Time Modulators Using SIMULINK-Based Time-Domain Behavioral Models , 2005 .

[4]  Ángel Rodríguez-Vázquez,et al.  High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  H. Aboushady,et al.  Automatic synthesis and simulation of continuous-time /spl Sigma//spl Delta/ modulators , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Ulf Schlichtmann,et al.  Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Belén Pérez-Verdú,et al.  CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom , 2006 .

[8]  M. Moyal,et al.  A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[9]  DebK.,et al.  A fast and elitist multiobjective genetic algorithm , 2002 .

[10]  E. Sanchez-Sinencio,et al.  A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[11]  Ángel Rodríguez-Vázquez,et al.  Analysis of clock jitter error in multibit continuous-time /spl Sigma//spl Delta/ modulators with NRZ feedback waveform , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[12]  Georges G. E. Gielen,et al.  A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  A. Rodríguez-Vázquez,et al.  Global design of analog cells using statistical optimization techniques , 1994 .

[14]  Georges G. E. Gielen,et al.  An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Hassan Aboushady,et al.  Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators , 2004, DATE.

[16]  W. Martin Snelgrove,et al.  Continuous-time delta-sigma modulators for high-speed a/d conversion , 2013 .

[17]  Georges Gielen,et al.  A behavioral simulation tool for continuous-time delta-sigma modulators , 2002, ICCAD 2002.

[18]  O. Yetik,et al.  A Coefficient Optimization and Architecture Selection Tool for ΣΔ Modulators in MATLAB , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Guido Stehr,et al.  Performance trade-off analysis of analog circuits by normal-boundary intersection , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[20]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[21]  M. Clara,et al.  A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution , 2004, IEEE Journal of Solid-State Circuits.

[22]  E. Sánchez-Sinencio,et al.  A Continuous-Time Modulator With 88-dB Dynamic Range and 1 . 1-MHz Signal Bandwidth , 2001 .

[23]  Georges G. E. Gielen,et al.  Efficient multiobjective synthesis of analog circuits using hierarchical Pareto-optimal performance hypersurfaces , 2005, Design, Automation and Test in Europe.

[24]  Lucien Breems,et al.  Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers , 2001 .

[25]  Richard Schreier,et al.  An empirical study of high-order single-bit delta-sigma modulators , 1993 .

[26]  Maurits Ortmanns,et al.  On the synthesis of cascaded continuous-time Sigma-Delta modulators. , 2001 .