Evaluating FPGA Virtex-II Board using Dynamic Partial Reconfiguration

The Field Programmable Gate Array (FPGA) offer effective suppleness and performance because of reconfigurable hardware but consume more power in contrast to the Application Specific Integrated Circuit (ASIC). At run time reconfiguration of hardware in FPGAs can not only be very economical but can be real alternative for ASICs. The designers are reluctant to use Dynamic Partial Reconfiguration (DPR) in FPGA due to lack of adequate tools provided by the vendors. DPR has been in academic use for more over a decade. DPR offers reduction in power consumption, area, cost as well as increase in flexibility, efficiency and fault tolerance but has an application dependent overhead. In this work prior performance of DPR is evaluated using Xilinx Virtex II Pro in order to realize whether it is suitable for an application rather than at later complex design stages of a system design having the DPR employed. The evaluation is based on the reconfiguration speed and the resource utilization. The DPR shows an improvement of resource utilization by 22.5 % (in terms of slices) as well as speedup in comparison to Non-DPR design. Keyword

[1]  Walter Stechele,et al.  A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[2]  Juanjo Noguera,et al.  Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[3]  Ahmed M. Eltawil,et al.  Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[4]  Ulrich Rückert,et al.  Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures , 2004, FPL.

[5]  Chang-Seok Choi,et al.  An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform , 2006, 2006 First International Conference on Communications and Electronics.

[6]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[7]  Apostolos Dollas,et al.  An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems , 2010, IEEE Transactions on Instrumentation and Measurement.

[8]  Eric Peskin,et al.  Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[9]  Bin Zhang,et al.  A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[10]  Eric McDonald.  Runtime FPGA Partial Reconfiguration , 2008, 2008 IEEE Aerospace Conference.

[11]  Pao-Ann Hsiung,et al.  Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures , 2008, TRETS.

[12]  Jürgen Becker,et al.  Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems , 2007, ReCoSoC.

[13]  Scott Hauck,et al.  Performance of partial reconfiguration in FPGA systems: A survey and a cost model , 2011, TRETS.

[14]  Chang-Seok Choi,et al.  A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform , 2007, IEICE Trans. Inf. Syst..

[15]  Jürgen Becker,et al.  Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs , 2008, 2008 Design, Automation and Test in Europe.