Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP

This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Application Specific Instruction-set Processor (ASIP). With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also various fast search algorithms. Moreover, the revisiting prevention technique enables that the proposed ASIP can efficiently perform the fast search operations. The gate count is 43K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with eight PEGs runs at 160MHz and can handle 1080p@30 frames in real-time.

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