Using positive feedback to overcome gmro limitations in scaled CMOS amplifier design
暂无分享,去创建一个
[1] R.H. Dennard,et al. Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.
[2] Anne-Johan Annema,et al. Analog circuit performance and process scaling , 1999 .
[3] Randall L. Geiger,et al. Positive feedback gain-enhancement techniques for amplifier design , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[4] B. Nauta,et al. Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.
[5] Randall L. Geiger,et al. A high gain strategy with positive-feedback gain enhancement technique , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[6] T.S. Kalkur,et al. High-speed current-mode logic amplifier using positive feedback and feed-forward source-follower techniques for high-speed CMOS I/O buffer , 2005, IEEE Journal of Solid-State Circuits.
[7] Robert H. Dennard,et al. Design of ion-implanted MOSFET's with very small physical dimensions , 2007 .
[8] J. Burleson,et al. Maximum intrinsic gain degradation in technology scaling , 2007, 2007 International Semiconductor Device Research Symposium.