Digital Encoders for High Speed Flash-ADCs: Modeling and Comparison
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[1] George Cybenko,et al. Approximation by superpositions of a sigmoidal function , 1992, Math. Control. Signals Syst..
[2] Jun Terada,et al. 8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).
[3] R. Perfetti,et al. Synthesis of feedforward neural analogue-digital convertors , 1991 .
[4] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[5] George Cybenko,et al. Approximation by superpositions of a sigmoidal function , 1989, Math. Control. Signals Syst..
[6] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .
[7] F. Kuttner,et al. A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.
[8] Kyusun Choi,et al. Fat tree encoder design for ultra-high speed flash A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[9] Mohamad Sawan,et al. A power efficient decoder for 2GHz, 6-bit CMOS flash-ADC architecture , 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).
[10] C.L. Portmann,et al. Power-efficient metastability error reduction in CMOS flash A/D converters , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..
[11] Michel Declercq,et al. New encoding scheme for high-speed flash ADC's , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[12] M.-C.F. Chang,et al. A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging , 2005, IEEE Journal of Solid-State Circuits.