INTEGRATED CIRCUIT DEVICE MISMATCH MODELING AND CHARACTERIZATION FOR ANALOG CIRCUIT DESIGN by
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[1] Alan Mathewson,et al. Optimizing MOS transistor mismatch , 1998, IEEE J. Solid State Circuits.
[2] Gabor C. Temes,et al. Random error effects in matched MOS capacitors and current sources , 1984 .
[3] R. Gregor,et al. On the relationship between topography and transistor matching in an analog CMOS technology , 1992 .
[4] W. Sansen,et al. Mismatch Characterization of Submicron MOS Transistors , 1997 .
[5] C. C. McAndrew,et al. A comprehensive vertical BJT mismatch model , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).
[6] S. Wolf,et al. Silicon Processing for the VLSI Era , 1986 .
[7] Marcel Pelgrom,et al. Matching properties of MOS transistors , 1988 .
[8] Shyh-Chyi Wong,et al. On matching properties and process factors for submicrometer CMOS , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[9] Mohammed Ismail,et al. Worst case analysis of low-voltage analog MOS integrated circuits , 1995, 38th Midwest Symposium on Circuits and Systems. Proceedings.
[10] H. P. Tuinhout,et al. The floating gate measurement technique for characterization of capacitor matching , 1996 .
[11] A.H. Montree,et al. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[12] M. Vertregt,et al. Test structures for investigation of metal coverage effects on MOSFET matching , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.
[13] Shyh-Chyi Wong,et al. Characterization and modeling of MOS mismatch in analog CMOS technology , 1995, Proceedings International Conference on Microelectronic Test Structures.
[14] J. S. Hunter,et al. Statistics for Experimenters: An Introduction to Design, Data Analysis, and Model Building. , 1979 .
[15] K. R. Lakshmikumar,et al. Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .
[16] G. Temes,et al. Random errors in MOS capacitors , 1982 .
[17] H. Elzinga. On the impact of spatial parametric variations on MOS transistor mismatch , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[18] Andreas G. Andreou,et al. Characterization of subthreshold MOS mismatch in transistors for VLSI systems , 1994, J. VLSI Signal Process..
[19] M. Vertregt,et al. Effects of metal coverage on MOSFET matching , 1996, International Electron Devices Meeting. Technical Digest.
[20] H. Su,et al. Yield optimization of analog MOS integrated circuits including transistor mismatch , 1993, 1993 IEEE International Symposium on Circuits and Systems.
[21] Mansun Chan,et al. A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation , 1997 .
[22] Marcel J. M. Pelgrom,et al. Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[23] M. Niewczas. Characterisation of the threshold voltage variation: a test chip and the results , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.
[24] Shinji Odanaka,et al. Influence of asymmetric/symmetric source/drain region on asymmetry and mismatch of CMOSFET's and circuit performance , 1998 .
[25] H. P. Tuinhout. Design of Matching Test Structures , 1994 .
[26] H. Elzinga. Using test structures to assess the impact of critical process steps on MOS transistor matching , 1998, ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157).
[27] F. Krummenacher,et al. A high density integrated test matrix of MOS transistors for matching study , 1998, ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157).
[28] A.J. Strojwas,et al. Using spatial information to analyze correlations between test structure data , 1990, International Conference on Microelectronic Test Structures.
[29] Shinji Odanaka,et al. Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.
[30] Michel Steyaert,et al. Statistics for matching , 1995, Proceedings International Conference on Microelectronic Test Structures.
[31] Mohammed Ismail,et al. A novel sensitivity analysis technique for VLSI statistical design , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[32] F. Forti,et al. Measurement of MOS current mismatch in the weak inversion region , 1994, IEEE J. Solid State Circuits.
[33] Michel Steyaert,et al. Threshold voltage mismatch in short-channel MOS transistors , 1994 .
[34] M. Bolt,et al. Matching properties of MOS transistors and delay line chains with self-aligned source/drain contacts , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[35] T. Serrano-Gotarredona,et al. Cheap and easy systematic CMOS transistor mismatch characterization , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[36] E. Parzen. 1. Random Variables and Stochastic Processes , 1999 .
[37] Mohammed Ismail,et al. Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits , 1993, 1993 IEEE International Symposium on Circuits and Systems.
[38] Shyh-Chyi Wong,et al. A CMOS mismatch model and scaling effects , 1997, IEEE Electron Device Letters.
[39] D. Marquardt. An Algorithm for Least-Squares Estimation of Nonlinear Parameters , 1963 .
[40] Hae-Seung Lee,et al. Characterization, modeling and minimization of transient threshold voltage shifts in MOSFETs , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[41] F.V. Fernandez,et al. Mismatch distance term compensation in centroid configurations with nonzero-area devices , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[42] W. F. Davis,et al. Statistical IC simulation based on independent wafer extracted process parameters and experimental designs , 1989, Proceedings of the Bipolar Circuits and Technology Meeting.
[43] S.D. Connor,et al. Automated extraction of matching parameters for bipolar transistor technologies , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[44] W. Sansen,et al. Mismatch characterization of small size MOS transistors , 1995, Proceedings International Conference on Microelectronic Test Structures.
[45] Michel Steyaert,et al. Matching of MOS transistors with different layout styles , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[46] H. Tuinhout,et al. Measurement of lithographical proximity effects on matching of bipolar transistors , 1998, ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157).
[47] Michel Steyaert,et al. Influence of die attachment on MOS transistor matching , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[48] Mohammed Ismail,et al. Statistical Modeling of Device Mismatch MOS Integrated Circuits for Analog , 1992 .
[49] Toru Toyabe,et al. A statistical model including parameter matching for analog integrated circuits simulation , 1985 .
[50] Alan Mathewson,et al. Characterizing the mismatch of submicron MOS transistors , 1996, Proceedings of International Conference on Microelectronic Test Structures.
[51] T. Serrano-Gotarredona,et al. A 'do-it-yourself' methodology for CMOS transistor mismatch characterization , 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.