Towards behavioral synthesis of asynchronous circuits - an implementation template targeting syntax directed compilation

This paper presents a method for behavioral synthesis of asynchronous circuits. Our approach aims at providing a synthesis flow which is very similar to what is found in existing synchronous design tools. We adapt the synchronous behavioral synthesis abstraction into the asynchronous handshake domain by introducing a computation model, which resembles the synchronous datapath and control architecture, but which is completely asynchronous. The datapath and control architecture is then expressed in the Balsa-language, and using syntax directed compilation a corresponding handshake circuit implementation is produced. The paper also reports area, speed and power figures for a couple of benchmark circuits, which have been synthesized to layout.

[1]  Jan Madsen,et al.  Power constrained high-level synthesis of battery powered digital systems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Jeong-Gun Lee,et al.  Automatic process-oriented control circuit generation for asynchronous high-level synthesis , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[3]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[4]  Niraj K. Jha,et al.  MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines , 1999 .

[5]  Ganesh Gopalakrishnan,et al.  Peephole optimization of asynchronous macromodule networks , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[7]  Steven M. Nowick,et al.  Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools , 2001 .

[8]  Kiyoshi Oguri,et al.  Asynchronous Circuit Design , 2001 .

[10]  Luciano Lavagno,et al.  Logic Synthesis for Asynchronous Controllers and Interfaces , 2002 .

[11]  D. A. Edwards,et al.  The Balsa Asynchronous Circuit Synthesis System , 2000 .

[12]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[13]  Erik Brunvand Translating concurrent communicating programs into asynchronous circuits , 1992 .

[14]  Van Berkel VLSI programming and silicon compilation , 1988 .

[15]  Jordi Cortadella,et al.  An asynchronous architecture model for behavioral synthesis , 1992, [1992] Proceedings The European Conference on Design Automation.

[16]  Ganesh Gopalakrishnan,et al.  High level synthesis of asynchronous circuit targeting state machine controllers , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[17]  Steven M. Nowick,et al.  Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems , 2002, DAC '02.

[18]  Marc Renaudin,et al.  A design framework for asynchronous/synchronous circuits based on CHP to HDL translation , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[19]  Chris J. Myers,et al.  Architectural synthesis of timed asynchronous systems , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).