New polynomial basis versatile multiplier over GF(2m) for low-power on-chip crypto-systems

This paper presents a low-power, reduced-area finite field multiplier over GF(2m) for ultra-low-power devices. The proposed design supports any field GF(2m) with low-weight irreducible polynomial. The different implementations presented in this paper support 99% of fields with prime m <; 4096. The proposed design is advantageous in terms of flexibility and hardware complexity. The design can perform multiplication over fields whose m > 1024, and all standard elliptic curves consuming 28.7μW and 4μW respectively, using the TSMC 65nm technology library. The design is demonstrated to operate at frequencies up to 500 MHz, allowing various trade-offs between power, energy and performance. The proposed design is shown to use around 40% less area and 40% less power than the other designs proposed in the literature. Hence, it enables implementing more secure ciphers for almost the lower cost than other available designs.