A divide-and-conquer approach to test generation for large synchronous sequential circuits

A method for generating tests for synchronous sequential circuits that does not use the complete circuit description is proposed, to allow true divide-and-conquer to be applied to test generation. The method is based on the generation of primary input sequences such that for as many sequences generated by the adjacent subcircuits as possible, a test sequence for the subcircuit under consideration would result. Repeated application of test sequences is proposed as a means of increasing the probability of fault detection. Experimental results are presented to show that the method is applicable to subcircuits of large sequential circuits.<<ETX>>

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