Comprehensive Design and Optimization of a High-Power-Density Single-Phase Boost PFC

The design of a single-phase boost power-factor-correction (PFC) circuit is associated with a large variety of considerations, such as the following questions. Which operation mode should be selected (e.g., continuous or discontinuous operation)? How many interleaved boost cells are advantageous? Which switching frequency should be selected? What is the optimum number of EMI input filter stages? Which semiconductor technology should be chosen? All these issues have a significant influence on the converter efficiency and power density. In this paper, the aforementioned questions are addressed for exemplary specifications of the PFC (300-W output power, 400-V output voltage, and 230-V mains voltage), whereby the focus in the design is mainly put on very high power density. As a result, different design points are identified and comparatively evaluated. By considering different aspects such as volume, losses, capacitor lifetime, and also cost issues (e.g., by additional current sensors or expensive silicon carbide devices), a dual-interleaved PFC operated in discontinuous conduction mode at 200 kHz is selected. With an experimental prototype, a superior power density of 5.5 kW/L and a system efficiency of 96.4% are achieved, which is close to the values predicted by the design procedure. Furthermore, measurements verify a near-unity power factor (PF = 99.7%) and the compliance with electromagnetic compatibility conducted noise emission standards. Finally, it is investigated to which extent the power density could be further increased by an integration of the input filter in the PCB.

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