Fast, Efficient and Predictable Memory Access: Optimization Algorithms for Memory Architecture Aware Compilation, Lars Wehmeyer, Peter Marwedel. Springer, Dordercht, The Netherlands (2006). 257pp., Hardcover, plus XI, ISBN: 1-4020-4821-1

Efficient memory design is a key bottleneck in embedded systems. An embedded memory system is a hierarchy of storage devices with different capacities, costs, and sizes. CPU registers hold the most frequently used data. Small, fast cache and scratch-pad memories, nearby the coreCPU, act as staging areas for subset of data and instructions, stored in the relatively slow main memory. The main memory stores data and code, relevant for correct system operation. Cost, power, and physical size forbid the use of virtual memory in a form of slow disks and other machines connected by networks. The memory hierarchy, as a critical determinant of overall system performance and power consumption, works because well-written programs tend to access the storage at any particular level more frequently than they access the storage of the next lower level. Memory system optimizations can target any stage of the memory hierarchy. During the last decade, large number of optimization techniques for onand off-chip memories have been developed. In essence, the possibility of customizing the target memory architecture and its associated data organizations reveals interesting theoretical and practical problems during embedded systems design. This nice book presents numerous techniques and methodologies primarily intended to design fast, energy efficient, and timing predictable memory systems implemented into embedded systems. It consists of eight chapters designed to capture the core ideas in embedded-memory design, References with 141 entries, and an Index. The book is organized as follows: Chapter 1 (Abstract, pp. 1–2) briefly involves the reader with the problems related to architectures and techniques, used in this book, intended to provide an energy efficient and fast memory accesses in modern embedded systems. Chapter 2 (Introduction, pp. 3–14) starts with a list of some typical embedded systems (handled devices, automotive/avionics, telecommunication) and points to their properties. After that, a general overview over the problems, which can be solved during the design of embedded systems, is exposed. Next, details concerning contributions of the work, presented in this book, are discussed. A short content description of each chapter is given in the last section. Chapter 3 (Models and Tools, pp. 15–88) concentrates on explanations of models and tools that are used to capture the properties of both processor and the memories from aspect of behavior, timing, and energy dissipation. More details concerning ISA-, timing-, energy-, and simulation-models are given. In the last section of this chapter the framework of the developed energy-aware compiler, called C compiler encc, which generates code for ARM 7 processor is described. Chapter 4 (Scratchpad Memory Optimizations, pp. 89– 169) is devoted to optimization techniques primarily targeted to efficiently manage the scratchpad memory (SPM), as small memory located at the same level in the memory hierarchy as level 1 cache, but managed by software. The main themes considered here are with multi memory optimization, and the impact of SPM allocation techniques on worst case execution time. Chapter 5 (Main Memory Optimizations, pp. 171–216) describes in more details two approaches used for power management of main memory. The discussion starts with presentation of the previous work concerning power management and saving energy in main memory. In the first approach, an energy model based on the standby energy of the main SDRAM memory is used to allocate memory objects to scratchpad in such a way that the main memory can be kept in energy-saving power-down mode for a maximum amount of time. The second approach relates to efficient utilization of a Flash memory used as an instruction memory. Chapter 6 (Register File Optimizations, pp. 217–232) points to the compiler responsibility for managing one of the most effective memories in the memory hierarchy: The register file. The main topics considered here are with implementation of the register file, register allocation and lifetime analysis, workflow and methodology, benchmark suite, and compiler guided choice of register file size. Chapter 7 (Summary, pp. 233–238) gives an overview of the complete work presented in this book, points to the possibilities of the proposed optimization techniques, and presents some general conclusions. Chapter 8 (Future Work, pp. 239–241) points to possible future research directions concerning the optimization of