High Performance and Low Leakage Design Using Cell Replacement and Hybrid V t Standard Cell Libraries

In recent years, the chip leakage power may be larger than the chip dynamic power because the semiconductor process technology progresses quickly. Therefore, leakage power reduction becomes an important issue for low power circuit designers. In this paper, we propose a heuristic cell replacement algorithm to reduce the leakage power of a logic design. The algorithm contains two procedures. The first one uses a conventional optimization approach and the second one uses a new optimization approach. In the first procedure, the algorithm uses high Vt, normal Vt, and low Vt cells to do cell replacement. In the second procedure, the algorithm employs hybrid threshold voltage standard cell libraries (HTVSCLs) to do cell replacement. The experimental results show that our technique can further reduce the leakage power up to 14.186% by using the second procedure after invoking the first procedure.