System level simulation guided approach to improve the efficacy of clock-gating

Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power reduction flow, automatic selection of appropriate registers and/or register banks is extremely time-consuming because power analysis is performed at the RTL or lower level. In a high-level synthesis (HLS) based design flow, to achieve faster design closure, one must be able to decide the appropriate set of registers to clock gate even before generating RTL. System-level simulations are known to provide faster simulation, yet there is no solution, which utilizes systemlevel simulation to provide guidance to HLS to create clock-gated RTL. Since predicting power reduction at higher levels of abstraction is difficult due to the dependence of power on physical details, an accurate and efficient relative power reduction model is required. In this paper, we propose a novel system-level design methodology, which utilizes a ‘relative power reduction model’ that can help in predicting the impact of clock-gating on each register/bank quickly and accurately, by simulating the design at a cycle accurate transaction-level. As a result, our approach can automatically find the appropriate registers to clock-gate, guided by the system-level simulation.