Compact Implementation of BLUE MIDNIGHT WISH-256 Hash Function on Xilinx FPGA Platform

This thesis proposes a hardware implementation of multivariate quadratic quasigroup (MQQ) public key cryptosystem that achieves decryption throughput of 399 Mbps on a Xilinx Virtex-5 field programable gate array (FPGA), which is running on 249.4 MHz. The encryption throughput of MQQ implementation achieves 44.27 Gbps on four Xilinx Virtex-5 chips that are running on 276.7 MHz. In addition for, the compact hardware implementation of Blue Midnight Wish (BMW) hash function, the thesis introduces a compact processing element on FPGA. Using the proposed processing element (PE), the BMW-256 has been implemented in just 51 FPGA slices achieving a throughput of 68.71 Mbps, and BMW-512 in just 105 slices, achieving a throughput of 112.18 Mbps. The PE requires the use of block RAM memory for storing the internal structure of hash functions, as well as for the PE instruction logic. Further, the thesis proposes FPGA implementations of a new transpose memory structure to be used in high throughput signal processing architectures. Simulation results show that the proposed memory allows a saving of 8 clock cycles per 8x8 block of discrete cosine transform (DCT) coefficients, compared to traditional implementations previously proposed by others. An important observation made during the design of this system is that it is easily integrable as an adaptive memory unit into modern coarse grained reconfigurable architectures, and upon modification can serve the dual role of a scratchpad register file as well as transpose memory during normal and digital signal processing (DSP) applications, respectively. Finally, the thesis proposes a robust scheme that uses digital invisible watermarking and hashing to protect the authorship of digital content, and provide resistance against malicious manipulation of multimedia content.