A HW/SW mixed mechanism to improve the dependability of a stack processor
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[1] Fabrice Monteiro,et al. A multiprocessor architecture for fast packet processing , 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.
[2] Fabrice Monteiro,et al. Stack processor architecture and development methods suitable for dependable applications , 2007, ReCoSoC.
[3] Dhiraj K. Pradhan,et al. Virtual Checkpoints: Architecture and Performance , 1992, IEEE Trans. Computers.
[4] M. Y. Hsiao,et al. A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .
[5] Luca Fossati,et al. A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).
[6] L. Alvisi,et al. A Survey of Rollback-Recovery Protocols , 2002 .
[7] Ahmed Amine Jerraya,et al. Programming models and HW-SW interfaces abstraction for multi-processor SoC , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[8] Chita R. Das,et al. Selective checkpointing and rollbacks in multi-threaded object-oriented environment , 1999 .
[9] Fabrice Monteiro,et al. A fault tolerant journalized stack processor architecture , 2009, 2009 15th IEEE International On-Line Testing Symposium.
[10] Carl E. Landwehr,et al. Basic concepts and taxonomy of dependable and secure computing , 2004, IEEE Transactions on Dependable and Secure Computing.
[11] Jr. Philip J. Koopman,et al. Stack computers: the new wave , 1989 .
[12] R.C. Baumann,et al. Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.