Design for testability issues in the implementation of sequential array architectures

New design for testability techniques aiming at overcoming the problem of testing array architectures composed of sequential cells are proposed. Two strategies have been envisioned: structural DFT techniques whose goal is to guarantee controllability and observability of the cell, and functional techniques aiming at defining an easily testable implementation at the FSM level and then synthesizing the modified functional description. Evaluation of the two classes of strategies on benchmarks are provided.<<ETX>>