Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus

A method of analog signal generation is presented that is suitable for most digital test methodologies such as that described by the IEEE 1149.1 test standard. The method can be used to produce a wide range of phase and frequency signals for system test debug and diagnosis. The method involves the generation of a 1-bit periodic bit stream through an off-chip software encoding procedure involving a delta-sigma modulator, followed by an on-chip hardware decoding procedure using a phase-locked loop and a circular register or memory. An experimental hardware prototype operating at 4 GHz implemented in a 0.13 ?m CMOS process will be used to illustrate the signaling capabilities of this generator under different test situations.

[1]  Henry Ott,et al.  Electromagnetic Compatibility Engineering , 2009 .

[2]  Gordon W. Roberts,et al.  A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehicles , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[3]  Gordon W. Roberts,et al.  A design, simulation and synthesis tool for delta-sigma-modulator-based signal sources , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[4]  Jean-Fu Kiang,et al.  A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Tsung-Hsien Lin,et al.  A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[6]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[8]  Y. A. Eken,et al.  A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[9]  Wei-Zen Chen,et al.  A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[10]  Ran-Hong Yan,et al.  A 13.4-GHz CMOS frequency divider , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[11]  Steve Weir Bypass Filter Design Considerations for Modern Digital Systems, A Comparative Evaluation of the Big "V", Multi-pole, and Many Pole Bypass Strategies" , 2005 .

[12]  Payam Heydari,et al.  Design of ultrahigh-speed low-voltage CMOS CML buffers and latches , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Sadok Aouini,et al.  Extending test signal generation using sigma-delta encoding beyond the voltage/amplitude domain , 2011 .

[14]  Gordon W. Roberts,et al.  A low-cost ATE phase signal generation technique for test applications , 2010, 2010 IEEE International Test Conference.

[15]  Tsung-Hsien Lin,et al.  Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- $N$ PLLs , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[17]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[18]  Howard C. Luong,et al.  A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Gordon W. Roberts,et al.  Frequency synthesis using digital-to-frequency conversion and filtering , 2010 .

[20]  Gordon W. Roberts,et al.  Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production , 2008, 2008 IEEE International Test Conference.

[21]  S. Pellerano,et al.  A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider , 2004, IEEE Journal of Solid-State Circuits.

[22]  Gordon W. Roberts,et al.  An integration of memory-based analog signal generation into current DFT architectures , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[23]  A. Rylyakov,et al.  A broadband 44-GHz frequency divider in 90-nm CMOS , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..

[24]  Sung Dae Lee,et al.  A high speed and low power phase-frequency detector and charge-pump , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[25]  Ching-Yuan Yang,et al.  A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13- $\mu\hbox{m}$ CMOS , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[27]  Ming-Dou Ker,et al.  Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13 /spl mu/m Cu-interconnection/low-k CMOS technology , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).