Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor
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Pradip Bose | Alper Buyuktosunoglu | Charles Johnson | Augusto Vega | Michele Franceschini | Robert K. Montoye | Jeff H. Derby
[1] H. Sloate,et al. Matrix representations for sorting and the fast Fourier transform , 1974 .
[2] H. Franke,et al. Introduction to the wire-speed processor and architecture , 2010, IBM J. Res. Dev..
[3] Robert K. Montoye,et al. VICTORIA: VMX indirect compute technology oriented towards in-line acceleration , 2006, CF '06.
[4] G. Fettweis,et al. ICT ENERGY CONSUMPTION – TRENDS AND CHALLENGES , 2008 .
[5] Christoforos E. Kozyrakis,et al. A case for intelligent RAM , 1997, IEEE Micro.
[6] John Cocke,et al. Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.
[7] Chen-Yong Cher,et al. A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[8] A. Glavieux,et al. Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.
[9] J. Tukey,et al. An algorithm for the machine calculation of complex Fourier series , 1965 .
[10] Toshio Nakatani,et al. AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors , 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).
[11] Pradip Bose,et al. Performance and power evaluation of an in-line accelerator , 2010, CF '10.
[12] Jah-Ming Hsu,et al. A parallel decoding scheme for turbo codes , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).