Hybrid $C$ – $V$ and $I$ – $V$ Technique for Separate Extraction of Structure- and Bias-Dependent Parasitic Resistances in a-InGaZnO TFTs

We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances (RS and RD) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, C- V and I -V measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness TIGZO , the gate length L, and the overlap length Lov between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component RH considering the transfer resistance RLT depending on the transfer length LT and the channel resistance RCH, as well as the vertical components in the S/D RVS and RVD. We confirmed the proposed technique through a separate extraction of VGS -independent contact resistances (RCS, RCD) from the channel length- and VGS-dependent RLT and RCH.