Research on the Fast Algorithm for Hierarchic Least Squares of Non-Negative Matrix Factorization

Non-negative matrix factorization is applied to in approximated nonlinear optimization for cost functions, thus we consider taking the mean square error as the cost function. Through the analysis of the amount of the iterative computation for layered alternated non-negative matrix factorization, we proposed an updates-limited method for consuming matrix operations in this paper to modify the iterative computation for layered alternated non-negative matrix factorization, therefore to achieve the purposes of accelerating the convergence. With simulation experiments, we compare the newly proposed algorithm with the original multiplication ones and projected gradient ones, and verify validity, stability, as well as the efficiency of the algorithm proposed in this paper.

[1]  Zhiping Yu,et al.  Impact of gate direct tunneling current on circuit performance: a simulation study , 2001 .

[2]  H. Iwai,et al.  1.5 nm direct-tunneling gate oxide Si MOSFET's , 1996 .

[3]  E. Vianello,et al.  Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays , 2007, IEEE Transactions on Electron Devices.

[4]  Rui Wang,et al.  The Informatization Development of Foreign Trade Enterprise in China: Case in Proceeding Trade , 2010, J. Digit. Content Technol. its Appl..

[5]  Chang Hong Lin,et al.  Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide , 2006 .

[6]  J. Wortman,et al.  Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices , 1999 .

[7]  S. E. Hosseini,et al.  An analytical gate tunneling current model for MOSFETs , 2012 .

[8]  Chen Wei-Bing,et al.  Analytic tunneling-current model of small-scale MOSFETs , 2006 .

[9]  M.J. van Duuren,et al.  Experimental characterization of statistically independent defects in gate dielectrics-part I: description and validation of the model , 2005, IEEE Transactions on Electron Devices.

[10]  Chih-Hung Chen,et al.  A review of gate tunneling current in MOS devices , 2006, Microelectron. Reliab..

[11]  A. Dutta,et al.  An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides , 2008, IEEE Transactions on Electron Devices.

[12]  Anni Cai,et al.  The Application of Spatio-temporal Feature and Multi-Sensor in Home Medical Devices , 2010, J. Digit. Content Technol. its Appl..