High Performance Memory Read Using Cross-Coupled Pull-up Circuitry
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[1] Shi-Yu Huang,et al. A low-power SRAM design using quiet-bitline architecture , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).
[2] G. Neuendorf,et al. Pipelined architecture for fast CMOS buffer RAMs , 1990 .
[3] Martin Margala. Low-power SRAM circuit design , 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.
[4] Thomas A. DeMassa,et al. Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.
[5] W. Paul,et al. Computer Architecture , 2000, Springer Berlin Heidelberg.
[6] Kiyoo Itoh. Low-voltage memories for power-aware systems , 2002, ISLPED '02.
[7] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[8] J.G. Delgado-Frias,et al. Reducing power and delay in memory cells using virtual source transistors , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..