Improvement of dual rail logic as a countermeasure against DPA

Dual rail logic is considered as a relevant hardware countermeasure against Differential Power Analysis (DPA) by making power consumption data independent. In this paper, we deduce from a thorough analysis of the robustness of dual rail logic against DPA the design range in which it can be considered as effectively robust. Surprisingly this secure design range is quite narrow. We therefore propose the use of an improved logic, called Secure Triple Track Logic, as an alternative to more conventional dual rail logics. To validate the claimed benefits of the logic introduced herein, we have implemented a sensitive block of the Data Encryption Standard algorithm (DES) and carried out by simulation DPA attacks.

[1]  George S. Taylor,et al.  Security Evaluation of Asynchronous Circuits , 2003, CHES.

[2]  Kjell Jeppson,et al.  Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay , 1994 .

[3]  Teresa H. Y. Meng,et al.  Automatic synthesis of asynchronous circuits from high-level specifications , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Srivaths Ravi,et al.  Security as a new dimension in embedded system design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  Marc Renaudin,et al.  DPA on quasi delay insensitive asynchronous circuits: formalization and improvement , 2005, Design, Automation and Test in Europe.

[6]  Alexander Chatzigeorgiou,et al.  Collapsing the transistor chain to an effective single equivalent transistor , 1998, Proceedings Design, Automation and Test in Europe.

[7]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[8]  Gilles Sicard,et al.  Statistic Implementation of QDI Asynchronous Primitives , 2003, PATMOS.

[9]  Daisuke Suzuki,et al.  Random Switching Logic: A Countermeasure against DPA based on Transition Probability , 2004, IACR Cryptol. ePrint Arch..

[10]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[11]  Robert H. Sloan,et al.  Examining Smart-Card Security under the Threat of Power Analysis Attacks , 2002, IEEE Trans. Computers.

[12]  Ingrid Verbauwhede,et al.  A VLSI design flow for secure side-channel attack resistant ICs , 2005, Design, Automation and Test in Europe.

[13]  Jean-Didier Legat,et al.  A Dynamic Current Mode Logic to Counteract Power Analysis Attacks , 2004 .

[14]  Ingrid Verbauwhede,et al.  Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology , 2003, CHES.

[15]  Mark G. Karpovsky,et al.  Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection] , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[16]  Ralph Howard,et al.  Data encryption standard , 1987 .

[17]  M. Robert,et al.  Evaluation of the robustness of dual rail logic against DPA , 2006, 2006 IEEE International Conference on IC Design and Technology.

[18]  Alexandre Yakovlev,et al.  Design and analysis of dual-rail circuits for security applications , 2005, IEEE Transactions on Computers.

[19]  Philippe Maurine,et al.  Transition time modeling in deep submicron CMOS , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[21]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .