A New Soft-Error Resilient Voltage-Mode Quaternary Latch
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[1] P. Glenn Gulak,et al. Look-up tables (LUTs) for multiple-valued, combinational logic , 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).
[2] N. Seifert,et al. Timing vulnerability factors of sequentials , 2004, IEEE Transactions on Device and Materials Reliability.
[3] P. K. Dakhole,et al. Low Power Quaternary CMOS Circuit Design , 2009, 2009 Second International Conference on Emerging Trends in Engineering & Technology.
[4] Y. Yagil,et al. A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[5] Zeljko Zilic,et al. Multiple-valued logic in FPGAs , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.
[6] Greg Atwood,et al. A multilevel-cell 32 Mb flash memory , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).
[7] Motoi Inaba. Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process , 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).
[8] S. Mahapatra,et al. Realization of multiple valued logic and memory by hybrid SETMOS architecture , 2005, IEEE Transactions on Nanotechnology.
[9] Vasundara Patel K.S.,et al. Quaternary CMOS Combinational Logic Circuits , 2009, 2009 International Conference on Information and Multimedia Technology.