Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry ☆

Active clamp circuits are essential to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and reliability requirements in high performance CMOS circuits. This paper discusses for the first time the electrostatic discharge (ESD) protection circuits of silicon-on-insulator (SOI) active clamp networks, dynamic threshold MOSFET SOI ESD techniques and the synthesis of DTMOS concepts, ESD protection networks and active clamp circuitry for high-pin-count high-performance semiconductor chips.

[1]  D.H. Allen,et al.  A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Steven H. Voldman.  The impact of MOSFET technology evolution and scaling on electrostatic discharge protection , 1998 .

[3]  Tak H. Ning,et al.  CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications , 1995, IBM Journal of Research and Development.

[4]  R. Gauthier,et al.  Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[5]  D. Kramer,et al.  A 580 MHz RISC microprocessor in SOI , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[6]  S.H. Voldman.  The impact of technology evolution and scaling on electrostatic discharge (ESD) protection in high-pin count high-performance microprocessors , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[7]  J.Y.-C. Sun,et al.  CMOS-on-SOI ESD protection networks , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[8]  F. Assaderaghi,et al.  Dynamic Threshold Body- And Gate-coupled SOI ESD Protection Networks , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[9]  S. S. Yuen,et al.  Comparison of ESD protection capability of SOI and bulk CMOS output buffers , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[10]  Chenming Hu.  Low-voltage CMOS device scaling , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[11]  G. Groeseneken,et al.  Analysis of Snapback in Soi nMosfets and its Use for an Soi Esd Protection Circuit , 1992, 1992 IEEE International SOI Conference.

[12]  Krishna Shenai,et al.  Scaling constraints imposed by self-heating in submicron SOI MOSFET's , 1995 .

[13]  Robin Williams,et al.  Electrostatic discharge protection in silicon-on-insulator technology , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[14]  E. Leobandung,et al.  Partially-depleted SOI technology for digital logic , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[15]  Sung-Mo Kang,et al.  EOS/ESD protection circuit design for deep submicron SOI technology , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[16]  C. Duvvury,et al.  ESD design for deep submicron SOI technology [NMOS transistor] , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[17]  Elyse Rosenbaum,et al.  Prediction of ESD protection levels and novel protection devices in thin film SOI technology , 1997 .

[18]  S. Ramaswamy,et al.  Heat flow analysis for EOS/ESD protection device design in SOI technology , 1997 .