Yearly update : exascale projections for 2013.

The HPC architectures of today are significantly different for a decade ago, with high odds that further changes will occur on the road to Exascale. This paper discusses the %E2%80%9Cperfect storm%E2%80%9D in technology that produced this change, the classes of architectures we are dealing with, and probable trends in how they will evolve. These properties and trends are then evaluated in terms of what it likely means to future Exascale systems and applications. 3

[1]  Hsien-Hsin S. Lee,et al.  Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[2]  Jack J. Dongarra,et al.  Performance of various computers using standard linear equations software in a FORTRAN environment , 1988, CARN.

[3]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[4]  Dirk Stroobandt,et al.  The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  E. Rent Memorandum to: File, Subject: Microminiature Packaging-Logic Block to Pin Ratio, December 12, 1960 , 2010, IEEE Solid-State Circuits Magazine.

[6]  Lei Jiang,et al.  Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[7]  Peter M. Kogge,et al.  Using the TOP500 to trace and project technology and architecture trends , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[8]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[9]  H LohGabriel 3D-Stacked Memory Architectures for Multi-core Processors , 2008 .

[10]  Bruce Jacob,et al.  Memory Systems: Cache, DRAM, Disk , 2007 .

[11]  Rick A. Rand,et al.  Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Betty Prince High Performance Memories: New Architecture DRAMs and SRAMs — Evolution and Function , 1996 .

[13]  Krisztián Flautner,et al.  PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor , 2006, ASPLOS XII.

[14]  Rajeev Balasubramonian,et al.  Leveraging 3D Technology for Improved Reliability , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[15]  David F. Heidel,et al.  An Overview of the BlueGene/L Supercomputer , 2002, ACM/IEEE SC 2002 Conference (SC'02).

[16]  Peter M. Kogge,et al.  On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications , 2007, IEEE Transactions on Computers.

[17]  Eun-Seok Choi,et al.  A Novel 3D Cell Array Architecture for Terra-Bit NAND Flash Memory , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[18]  Yiran Chen,et al.  A novel architecture of the 3D stacked MRAM L2 cache for CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[19]  Norman P. Jouppi,et al.  Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).