Low-Power Digital Filtering Based on the Logarithmic Number System

This paper investigates the use of the Logarithmic Number System (LNS) as a low-power design technique for signal processing applications. In particular we focus on power reductions in implementations of FIR and IIR filters. It is shown that LNS requires a reduced word length compared to linear representations for cases of practical interest. Synthesis of circuits that perform basic arithmetic operations using a 0.18µm 1.8V CMOS standard-cell library, reveal that power dissipation savings more than 60% in some cases are possible.

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