FPGA Implementation of Spatial Image Filters using Xilinx System Generator

Abstract The objective of this paper is to design, model, simulate and synthesis of Spatial Filtering Techniques, in which the operation is performed within neighborhood of a pixel. Recent increases in Filed Programmable Gate Array (FPGA) performance and size offer a new hardware acceleration opportunity. The convolution filtering operations are implemented using Xilinx System Generator (XSG) which is the industry's leading high-level tool for designing high-performance DSP systems using FPGAs. The designs are modeled using XSG Block set and synthesized onto Virtex 6 xc6vs315t-3ff156 FPGA device. The algorithms are validated using hardware co-simulation method.