论文信息 - Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

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