A subpicosecond jitter PLL for clock generation in 0.12-/spl mu/m digital CMOS

A fully integrated subpicosecond jitter phase-locked loop (PLL)-based frequency synthesizer in a standard digital 0.12-/spl mu/m CMOS technology with 1.5-V supply is presented. Two differentially tuned LC-VCOs are implemented to support different standards for serial data transmission. A fully differential charge pump and an active loop filter are used for reduction of charge-pump current mismatch. Operating with a 311-MHz reference clock, the PLL achieves typically 860-fs integrated jitter, and a phase noise of -115 dBc/Hz at 1-MHz offset, on a 2.488-GHz output. The power consumption is 35 mW, and the area is 0.7 mm/sup 2/.

[1]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[2]  Andreas Wiesbauer,et al.  On the jitter requirements of the sampling clock for analog-to-digital converters , 2002 .

[3]  P.R. Gray,et al.  A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[4]  Keh-Chee Jen,et al.  Fully-integrated SONET OC48 transceiver in standard CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .