ADC in 90 nm CMOS

gain and the dynamic range of the ADC. Use of high speed and high resolution ADCs for wireless receivers, allows part of the analog channel filtering and VGA functions to be performed in the digital domain, and results in reduced complexity and reduced silicon area of the analog baseband circuits, which is suitable for CMOS process scaling. Furthermore, the smaller the maximum VGA gain is, the easier the implementation of a DC offset cancellation circuit is, which is indispensable for direct-conversion receivers. The ADC should be integrated on the OFDM IC, so that analog differential signals from I and Q-channel VGAs are used as interface signals between the RF IC and the OFDM IC, and thus the number of the interface signals are minimized. A triple-sampling technique and a two-step summation scheme are applied to improve the linearity of the ADC with low power consumption [2], [3]. Also, a low voltage bandgap reference and a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is designed and implemented on the same process. The ADC achieves a 66.85 dB peak SNDR over a 4 MHz bandwidth while consuming 6.9 mA from a 1.2 V supply and 1.16 mA from 3.3 V supply. The achieved figure of merit (FOM) of the ADC is 0.82 pJ/conversion, which is defined as

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