Computer-aided design-for-reliability of deep sub-micron integrated circuits

The last few years have witnessed a revolution in integrated circuit (IC) fabrication technology leading to high packing densities of ICs. Although this has paved the way for increased portability and faster clock rates, it has also given rise to new problems. One such is the increased unreliability in deep sub-micron ICs. In this dissertation, we address reliability concerns that are caused by soft errors, electromigration (EM) and hot-carriers effects within a top-down design methodology. Traditionally reliability has been addressed late in the design process (usually at the device and circuit levels). At this stage, improvements in reliability are obtained at the cost of degradation in performance already incorporated earlier in the IC design process. This results in wasted design effort and increased time-to-market. In this dissertation, we propose novel techniques that enhance IC reliability. (1) Soft errors are minimized at the system level by suitably synthesizing a multiprocessor for an application task graph. (2) Electromigration induced failures are reduced at the RT level by suitably sequencing the data-transfers onto buses. (3) Hot-carrier induced damage is minimized at the switch level by suitably reordering the inputs to the logic gates and by resizing the hot-carrier affected MOSFETs. The proposed techniques for reliability enhancement were evaluated on benchmark examples. High-reliability designs are synthesized subject to constraints on delay, energy dissipation and area. Finally, the results are validated by simulating the synthesized reliability-optimized circuits.