An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects

We propose a new and efficient statistical-simulation-based test methodology for optimally selecting repair elements at beginning-of-life (BOL) to improve the end-of-life (EOL) functionality of memory designs. This is achieved by identifying the best BOL test/repair corner that maximizes EOL yield, thereby exploiting redundancy to optimize EOL operability with minimal BOL yield loss. The statistical approach makes it possible to identify such corners with tremendous savings in terms of test time and hardware. To estimate yields and search for the best repair corner the approach relies on fast conditional importance sampling statistical simulations. The methodology is versatile and can handle complex aging effects with asymmetrical distributions. Results are demonstrated on state-of-the-art dual-supply memory designs subject to statistical negative bias temperature instability (NBTI) effects, and hardware results are shown to match predicted model trends.

[1]  R.V. Joshi,et al.  A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[2]  Rouwaida Kanj,et al.  Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell , 2006, 2006 European Solid-State Device Research Conference.

[3]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[5]  R. Wong,et al.  Impact of NBTI Induced Statistical Variation to SRAM Cell Stability , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[6]  Sani R. Nassif Design for Variability in DSM Technologies , 2000 .

[7]  Wei Chen,et al.  The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series , 2007, IEEE Journal of Solid-State Circuits.

[8]  W. Weibull A Statistical Distribution Function of Wide Applicability , 1951 .

[9]  S. Rauch,et al.  Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.

[10]  Ching-Te Chuang,et al.  Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[11]  M. Agostinelli,et al.  6-T cell circuit dependent GOX SBD model for accurate prediction of observed vccmin test voltage dependency , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.