New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

[1]  S. Martello,et al.  Exact Solution of the Two-Dimensional Finite Bon Packing Problem , 1998 .

[2]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[3]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Marco Platzner,et al.  Fast online task placement on FPGAs: free space partitioning and 2D-hashing , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[5]  Samir I. Shaheen,et al.  Improving utilization of reconfigurable resources using two dimensional compaction , 2007 .

[6]  Hartmut Schmeck,et al.  Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer , 2000, FPL.

[7]  Klaus Danne,et al.  Off-Line Placement of Tasks onto Reconfigurable Hardware Considering Geometrical Task Variants , 2005, IESS.

[8]  Diederik Verkest,et al.  Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems , 2003, FPL.

[9]  J. Clausen,et al.  Branch and Bound Algorithms-Principles and Examples , 2003 .

[10]  Tamás Vinkó,et al.  A comparison of complete global optimization solvers , 2005, Math. Program..

[11]  Ranga Vemuri,et al.  An efficient algorithm for finding empty space for online FPGA placement , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Andrea Lodi,et al.  Two-dimensional packing problems: A survey , 2002, Eur. J. Oper. Res..

[13]  Edward G. Coffman,et al.  Approximation algorithms for bin packing: a survey , 1996 .

[14]  Jin-Kao Hao,et al.  Métaheuristiques pour l'optimisation combinatoire et l'affectation sous contraintes , 1999 .

[15]  Georgi Gaydadjiev,et al.  Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems , 2008, 2008 Design, Automation and Test in Europe.

[16]  Jürgen Teich,et al.  A new approach for on-line placement on reconfigurable devices , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[17]  Nadeem Daudpota,et al.  Parallel Branch and Bound Model Using Logarithmic Sampling (PBLS) for Symmetric Traveling Salesman Problem , 2007 .

[18]  Ronald L. Rivest,et al.  Orthogonal Packings in Two Dimensions , 1980, SIAM J. Comput..

[19]  Gabor Pataki,et al.  Basis reduction and the complexity of branch-and-bound , 2009, SODA '10.

[20]  Carlos González,et al.  A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[21]  E. Panainte,et al.  FPGA-area Allocation for Partial Run-Time Reconfiguration , 2005 .

[22]  Ikbel Belaid,et al.  Off-line placement of hardware tasks on FPGA , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[23]  Majid Sarrafzadeh,et al.  3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems , 2000, Des. Autom. Embed. Syst..

[24]  Jürgen Teich,et al.  Optimization of Dynamic Hardware Reconfigurations , 2004, The Journal of Supercomputing.

[25]  Daniele Vigo,et al.  Heuristic and Metaheuristic Approaches for a Class of Two-Dimensional Bin Packing Problems , 1999, INFORMS J. Comput..

[26]  Daniele Vigo,et al.  Neighborhood Search Algorithm for the Guillotine Non-Oriented Two-Dimensional Bin Packing Problem , 1999 .

[27]  Daniel Chillet,et al.  Flexible communication support for dynamically reconfigurable FPGAS , 2009, 2009 5th Southern Conference on Programmable Logic (SPL).