System architecture implications of 3-D interconnect technologies

We compare and contrast three different 3-D packaging approaches, and examine their impact on the architecture of digital systems. As a baseline, we use a conventional multi-board approach. One 3-D system, recently developed at HiDEC, involves the use of dense (.5 mm pitch) area array Z-axis connectors between multichip substrates populated with flip chip digital elements. It is shown from Rent's Rule considerations that a system of this kind is restricted to bus-type interconnections among the vertical elements. Nevertheless, this type of physical architecture is useful for massively parallel system architectures, in which one or more processing elements are completely contained on a given physical layer. A second 3-D approach uses thin silicon ICs, flip chip attached to thin flex interposers, which are then assembled as layers using some form of conductive paste interconnects, again at .5 mm area array pitch. In this case, tight vertical spacing can reduce interconnect length and delay, but Rent's Rule constraints still limit the number of gates that can be used in a given processing element. The third system uses through-silicon vias on thin integrated circuit elements to allow the direct stacking of multiple ICs. This method offers the potential of 10 μm vias on 20 μm pitch through ICs thinned to 50 μm. Again using Rent's Rule considerations and current IC gate densities, we show that block-to-block random logic numbers of interconnects can be made among the different IC layers in the stack. The dense interconnection of logic blocks separated by only 55 pm in the Z axis can substantially reduce the RC delays of long interconnects on a large planar IC. Moreover, significant reductions in average interconnect length would also reduce IC power dissipation in interconnect charge/discharge cycles. We describe the potential system characteristics using this composite IC technology.